Post on Arthur's blog

Rust firmware tools: rflasher and rem100

Tue, 24 Feb 2026 17:24:40 +0100

After the serprog adventures with Embassy on microcontrollers, it was time to tackle the host side of firmware tooling. Two tools that come up constantly in firmware development are flashprog for reading and writing SPI flash chips, and the Dediprog EM100Pro tool for controlling the EM100 SPI flash emulator. Both are C tools that have been around for a while. We ported both to Rust: rflasher and rem100. On top of that, both now have browser-based WebUIs that run as pure WASM with no server-side processing.

Vibe Coding an Emacs-Style Hugo Theme

Mon, 02 Feb 2026 00:00:00 +0000

I've been using hugo-theme-terminal for my blog and really liked its clean, terminal-inspired aesthetic. But as someone who spends most of their day in Emacs, I wanted something that felt more like home.

So I vibe coded an Emacs-style theme with Claude. The entire thing - HTML templates, CSS, JavaScript interactions - was built through conversation with AI.

Features

Dired-style article list with reading time, word count, and dates
Window splitting with C-x 2 (vertical) and C-x 3 (horizontal)
Navigate with n/p, open with RET, go back with q
Modus Vivendi (dark) and Modus Operandi (light) themes, toggle with t
Emacs modeline showing buffer name, scroll position, and mode
Even has a working menu bar

The Result

The theme is available at github.com/ArthurHeymans/hugo-emacs-theme.

Experimenting with a faster TRAMP backend using Rust and JSON-RPC

Fri, 16 Jan 2026 11:23:08 +0100

TRAMP is one of Emacs' killer features. The ability to transparently edit files on remote machines, run shells, and use version control as if everything were local is remarkable. The implementation is impressively portable - it works over SSH, sudo, docker, and countless other methods by cleverly parsing shell command output.

I've been experimenting with an alternative approach that trades some of TRAMP's universality for speed improvements in the common SSH use case. This is very much an alpha project and nowhere near as battle-tested as TRAMP, but the early results are promising enough that I wanted to share it and get feedback.

Sending receipts to my accountant from Emacs

Thu, 11 Dec 2025 14:19:22 +0100

Living inside Emacs is a dream - email, git, project management, writing, coding all in one environment. But every so often, something forces you back to a web browser. Uploading receipts to my accountant through ClearFacts was one of those moments.

Every month, receipts and invoices accumulate that need to reach my accountant. ClearFacts provides an API for this, but the journey from documentation to working solution proved more interesting than expected.

My first emacs package: lsp-cargo-feature-switcher

Thu, 16 Oct 2025 18:16:52 +0200

This explains how to properly configure LSP Rust features in Emacs and introduces an interactive tool for managing them.

Glossary

rust-analyzer: The LSP server for Rust that provides IDE-like features in editors.
Cargo features: Conditional compilation flags in Rust projects defined in Cargo.toml.
LSP: Language Server Protocol, providing language intelligence to editors.
.dir-locals.el: Emacs mechanism for setting directory-local variables.

The wrong way and the right way

In my previous post Making Emacs LSP work with Rust conditional features, I suggested using safe-local-variable-values to bypass Emacs' safety prompts for LSP rust features. That approach was wrong. The code I suggested:

Adding MCP support to Aider via NixOS overrides

Thu, 03 Jul 2025 16:29:32 +0200

In software engineering the part I like the least is the actual typing of coding. LLMs provide a nice solution to this problem. With very precise prompting and the right documentation, code, text, … in the context the code output is very close to how I would write it.

My preferred tool until now was aider. It works great, but the development pace seems to have slowed sadly. One of the latest innovation in the vibe coding space has been model context protocol. MCP is basically a standardized way to provide tools to LLMs and the majority of the AI coding agents are using it.

Making Emacs LSP work with Rust conditional features

Wed, 11 Jun 2025 11:23:17 +0200

So here is where it all started. I'm working on a Rust project that makes heavy use of conditional compilation through cargo features. The codebase has chunks of code that are only compiled when certain features are enabled, like this:

#[cfg(feature = "generate_templates")]
mod cert;
#[cfg(feature = "generate_templates")]
mod code_gen;
#[cfg(feature = "generate_templates")]
mod csr;

#[cfg(feature = "generate_templates")]
fn gen_init_devid_csr(out_dir: &str) {
 // ... implementation
}

The problem? My trusty Emacs LSP setup was giving me a cold shoulder on all this conditional code. No completions, no error checking, no "go to definition" - basically treating it like it doesn't exist. And technically, it's right! By default, rust-analyzer only analyzes code with the default set of features enabled.

Serprog adventures in rust

Sat, 24 May 2025 10:44:02 +0200

Serprog

Serprog is a serial flasher protocol that allows a userspace program like flashprog to communicate over a serial connection like RS232, USB endpount or a TCP stream to a microcontroller which talks to flash chip to read, write or erase it. Serprog works for all kinds of different flash chips but in this article we'll focus on SPI NOR since those are ubiquitous nowadays.

Picoprog at OSFC: using embassy as a multifunction device

For OSFC 2024, 9elements hosted a coreboot workshop, which involved compiling coreboot and flashing it onto a Raxda x4 N100 board. To flash it and get uart output we needed some hardware. We thought it would be fun to create our own and allow people to take it home. We used an off the shelf Raspberry Pi Pico and designed a breakout board which makes it easy to attach a SPI clip and connect the boards UART pins.

probe-rs: Making Embedded Development Feel Like Userspace Programming

Sat, 24 May 2025 10:03:20 +0200

If you've ever developed embedded firmware, you know the pain: cryptic flashing tools, primitive debugging methods, and a workflow that feels decades behind modern software development. You write code, compile it, flash it to hardware through a complex toolchain, and then… hope it works. When it doesn't, you're stuck with blinking LEDs and printf debugging over UART. probe-rs fundamentally changes this experience by bringing the productive, familiar workflow of userspace development to the embedded world.

Panics in rust and how to track them

Thu, 19 Dec 2024 20:11:27 +0100

Introduction to panics in rust

Undefined behavior (UB) is one of the most dangerous issues in systems programming, leading to crashes, security vulnerabilities, and unpredictable results. Rust prevents UB by panicking - forcefully stopping the program - when potentially unsafe operations are detected.

Panics are Rust's way of handling unrecoverable errors. Unlike Result which handles expected errors, panics occur when:

Array bounds are exceeded
Integer overflow in debug mode
Explicit calls to panic!() macro
Failed assertions
Calling unwrap() on None or Err values
Attempting operations that may cause undefined behavior

Key points about panics:

Ontology in Software Programming: Understanding the Nature of What We Build

Mon, 09 Dec 2024 12:16:52 +0100

As software developers, we spend our days creating objects, defining relationships, and modeling reality in code. But have you ever stopped to think about the philosophical implications of what we're doing? Enter ontology – a branch of philosophy that deals with the nature of being, existence, and reality.

Understanding Ontology

In philosophy, ontology asks fundamental questions like "What exists?" and "What are the relationships between different things that exist?" These might sound abstract, but as programmers, we deal with similar questions every day. When we create a class hierarchy or design a database schema, we're actually doing ontological work – we're defining what "exists" in our software universe and how these things relate to each other.

Getting Hypridle to work with Hyprlock

Thu, 05 Dec 2024 09:09:17 +0100

I recently switched from Sway to Hyprland. The primary reason for this change was my interest in content creation. Hyprland can record single windows, whereas Sway can only record the entire screen or part of it.

So far, the transition has been smooth until I encountered the following issue after waking it from suspend with the lid closed.

My Use Case

I have a laptop that is mostly connected to a docking station driving an external display. The lid remains closed, and I don't want the laptop display enabled. When no display is connected, I want the device to suspend. This is managed by logind.

Using LLMs in emacs

Wed, 06 Nov 2024 08:34:52 +0100

This post will review 2 llm options in emacs how I set them up.

Ellama

Your browser does not support the video tag.

From ellama

Ellama is a tool for interacting with large language models from Emacs. It allows you to ask questions and receive responses from the LLMs. Ellama can perform various tasks such as translation, code review, summarization, enhancing grammar/spelling or wording and more through the Emacs interface. Ellama natively supports streaming output, making it effortless to use with your preferred text editor.

rtimer: Writing a Timer with Aider

Mon, 21 Oct 2024 00:00:00 +0000

Aider + Claude Sonnet 3.5

This morning, I needed a timer to spend only 10 minutes reading a book. I searched for CLI tools but couldn't find anything immediately that suited my needs due to laziness. So, I decided to write one myself with the help of AI.

Using Aider coupled with Claude Sonnet 3.5, I was able to get something working on the first try. Afterward, I added a few features:

A comparison between open source host firmware solutions and closed source UEFI

Wed, 28 Feb 2024 13:14:08 +0100

This whitepaper makes the case that UEFI firmware and more specifically EDK2 based solutions, be it open or the more ubiquitous closed ones, hurt business by driving up cost and delaying time to market, while at the same time are the root cause of more and more security problems. This whitepaper will contrast this UEFI status quo with other existing solutions like LinuxBoot in combination with coreboot, which fully embrace open source development, are scoring better on all those metrics. This is both due to design decisions and the related development models.

Integrating rust in coreboot: baby steps

Tue, 01 Aug 2023 00:00:00 +0000

Rust in coreboot?

Rust is a programming language with emphasis on performance, type safety and concurrency. It enforces memory safety at compile time. Unlike the C standard which is a 700+ page document, with a LOT of documented undefined behavior, rust has no undefined behavior unless the unsafe keyword is used. Zero cost abstractions make rust binaries very efficient in both size and execution, in places where C will have a hard time to be optimized (e.g. function pointers in structs).

Coreboot on the ASRock E3C246D4I

Thu, 15 Jul 2021 00:00:00 +0000

This blog enty first appeared on the 9esec blog.

A new toy to play with OpenBMC

I wanted to play around with OpenBMC on a physical board and this article led me to the ASRock E3C246D4I. It's a not overly expensive Intel Coffee Lake board featuring an Aspeed AST2500 BMC. So the first thing I did was to compile OpenBMC. My computer was in for a quite a chore there. It needed to download 11G of sources and compile those. Needless to say this takes a long time on a notebook computer and is best done overnight. I flashed the image via the SPI header next to the BMC flash. I used some mini crocodile clips to do this at first.

Open source cache as ram with Intel Bootguard

Fri, 25 Jun 2021 00:00:00 +0000

This blog enty first appeared on the 9esec blog.

FSP-T in open source projects

X86 CPUs boot up in a very bare state. They execute the first instruction at the top of memory mapped flash in 16 bit real mode. DRAM is not avaible (AMD Zen CPUs are the exception) and the CPU typically has no memory addressable SRAM, a feature which is common on ARM SOCs. This makes running C code quite hard because you are required to have a stack. This was solved on x86 using a technique called cache as ram or CAR. Intel calls this non eviction mode or NEM. You can read more about this here.

Hardware assisted root of trust mechanism and coreboot internals

Wed, 26 May 2021 00:00:00 +0000

This blog enty first appeared on the 9esec blog.

I started working for 9elements in October 2020 and my first assignment was to get Intel CBnT working on the OCP Deltalake using coreboot firmware. Intel Converged Bootguard and TXT is a hardware assisted method to set up a root of trust. In this blog post I will discuss some of the changes needed in coreboot to get this working. Setting CBnT up properly was definitely a challenge, but the work did not stop there. So while Intel CBnT provides a method to verify or measure the initial start-up code, it is not enough. You want to trust the code you run from start, the reset vector, to end, typically a bootloader. CBnT only takes care of the start. You have to make sure that each software component trusts the assets it uses and the next program it loads. This concept is called a chain of trust. Now in 2021 I have an assignment that involves supporting the older Intel Bootguard technology. Since Bootguard is very similar to CBnT, I'll also touch on that.

FSP1.1 Braswell TempRaminit problems

Sat, 23 Nov 2019 00:00:00 +0000

Coreboot is migrating platforms from a romcc bootblock to C_ENVIRONMENT_BOOTBLOCK in which Cache-as-Ram is set up in the bootblock. When migrating Braswell, chromebooks featuring this SOC did not boot anymore while other boards did. Google uses a different FSP binary than the one present in the Intel Github FSP repository.

Previously the romcc bootblock set up caching of the ROM, located microcodes and performed the update before calling FSP TempRaminit.

A gentle introduction to Cache-as-Ram on X86

Wed, 23 Oct 2019 00:00:00 +0000

This explains a bit of history on CAR in coreboot and how it works.

Glossary

CPU cache: CPU cache is a piece of fast memory used by the CPU to cache access to things accessed in the CPU's linear memory space. This includes for DRAM, PCI BARs, the boot flash.
Cache-as-RAM/CAR: Using not memory mapped CPU cache as execution environment.
XIP: Execute in place on a memory mapped (read only) medium.
SRAM: Static Random Access Memory, here: memory mapped memory that needs no initialization.
ROMCC: A C compiler using only the CPU registers.

Cache-as-Ram, the basics

When an X86 platforms boot, it starts in a pretty bare environment. The first instruction is fetched from the top of the boot medium, which on most x86 platforms is memory mapped below 4G (in 32bit protected mode). Not only do they start in 16bit 'real' mode, most of the hardware starts uninitialized. This includes the dram controller. Another thing about X86 platforms is that they generally don't feature SRAM, static RAM. SRAM for this purpose of this text is a small region of ram that is available without any initialization. Without RAM this leaves the system with just CPU registers and a memory mapped boot medium of which code can be executed in place (XIP) to initialize the hardware.

How to flash coreboot to the thinkpad x60 the proper way

Sat, 01 Dec 2018 00:00:00 +0000

What is so special about the x60 when running vendor bios?

Vendor BIOS write protects its bootblock, which means the lowest 64K of the flash can’t be modified

This is a problem since the first code that runs on the CPU comes from there and if we ever want to run coreboot the cpu must start with coreboot code. This write protection is set in the PBR (protect bios range) registers on the southbridge, there is currently no known way to change them back once they are locked by setting the SPI Configuration Lock-Down bit.

Hacking ath9k wifi device adventures

Sat, 03 Nov 2018 00:00:00 +0000

So here is where it all started. I have this apple branded atheros AR5BXB92, with an ar9280 chipset, which is supported by the ath9k Linux drivers. This chipset is supposed to support both 5GHz and 2.4GHz frequencies, but using the wavemon tool 5GHz SSID never show up even when I'm next to a device that emits one.

iw list shows the following:

Band 2:
 Capabilities: 0x11ce
 HT20/HT40
 SM Power Save disabled
 RX HT40 SGI
 TX STBC
 RX STBC 1-stream
 Max AMSDU length: 3839 bytes
 DSSS/CCK HT40
 Maximum RX AMPDU length 65535 bytes (exponent: 0x003)
 Minimum RX AMPDU time spacing: 8 usec (0x06)
 HT TX/RX MCS rate indexes supported: 0-15
 Bitrates (non-HT):
 * 6.0 Mbps
 * 9.0 Mbps
 * 12.0 Mbps
 * 18.0 Mbps
 * 24.0 Mbps
 * 36.0 Mbps
 * 48.0 Mbps
 * 54.0 Mbps
 Frequencies:
 * 5180 MHz [36] (16.0 dBm) (no IR)
 * 5200 MHz [40] (16.0 dBm) (no IR)
 * 5220 MHz [44] (16.0 dBm) (no IR)
 * 5240 MHz [48] (16.0 dBm) (no IR)
 * 5260 MHz [52] (17.0 dBm) (no IR, radar detection)
 * 5280 MHz [56] (16.0 dBm) (no IR, radar detection)
 * 5300 MHz [60] (16.0 dBm) (no IR, radar detection)
 * 5320 MHz [64] (16.0 dBm) (no IR, radar detection)
 * 5500 MHz [100] (disabled)
 * 5520 MHz [104] (disabled)
 * 5540 MHz [108] (disabled)
 * 5560 MHz [112] (disabled)
 * 5580 MHz [116] (disabled)
 * 5600 MHz [120] (disabled)
 * 5620 MHz [124] (disabled)
 * 5640 MHz [128] (disabled)
 * 5660 MHz [132] (disabled)
 * 5680 MHz [136] (disabled)
 * 5700 MHz [140] (disabled)
 * 5745 MHz [149] (disabled)
 * 5765 MHz [153] (disabled)
 * 5785 MHz [157] (disabled)
 * 5805 MHz [161] (disabled)
 * 5825 MHz [165] (disabled)

So most of the 5GHz channels which are avaible in my country were disabled. Changing the reg domain iw reg set BE did not change this On the web I found some articles about modifying the reg domain in the eeprom that is present on that wifi card. One of these is the following guide. The link to the iwleeprom code is dead but can be found on the following github repo. Doing so I found out that my region code is 0x65. I tried to modify that eeprom content but that didn't seem to work properly for some reason. I knew that almost everything is done by the kernel driver so I looked for the possibilty to override this regional setting an I found it! By changing the reg_rules for my 0x65 domain device and recompiling the ath9k module I got those 5GHz appearing in wavemon and listed as supported in iw list!

Porting the Intel DG41WV and Intel 4 series DDR3 raminit to coreboot

Sat, 03 Nov 2018 00:00:00 +0000

This post will explain a bit how the Intel 4 series DDR3 raminit came to be and will introduce a new board that can make use of this code, namely the Intel DG41WV.

DDR3 raminit

In the past I have worked quite on a bit on the coreboot code that support the Intel 4 series desktop chipset (those chipsets go by the name of G41, G43, G45, Q43, Q45, P41, P43, P45, B43 with each having a somewhat different feature set). In the past I have made quite a few improvements to the coreboot code for this platform: