The board I chose to develop the DDR3 raminit on was an Intel DG41WV. I chose it for a few reasons:
- It was cheap
- It had a socket (DIP8) spi flash which makes reflashing easy and avoid unexpected electrical difficulties which might require desoldering it.
- It has a SuperIO supported by coreboot
- It has a serial port
Obviously getting the ram to work was by far the largest part of this port. The board port part is usually really small and with some experience it can usually be done in a few hours. The DG41WV was no different in that aspect. One peculiarity was that the on the VGA output the display was garbled. I had this problem on other boards before and is typically an issue with the default clockgen configuration having a wrong clock frequency for the VGA output. Publicly available documentation for CK505 clockgens is scarce so one solution is to program whatever vendor has set.
First figure out on which number Linux maps the SMBUS:
modprobe i2c-dev
i2cdetect -l
The result will look like:
i2c-3 i2c i915 gmbus dpc I2C adapter
i2c-1 i2c i915 gmbus vga I2C adapter
i2c-8 i2c DPDDC-D I2C adapter
i2c-6 i2c DPDDC-B I2C adapter
i2c-4 i2c i915 gmbus dpb I2C adapter
i2c-2 i2c i915 gmbus panel I2C adapter
i2c-0 i2c i915 gmbus ssc I2C adapter
i2c-9 smbus SMBus I801 adapter at 0400 SMBus adapter (this is the one)
i2c-7 i2c DPDDC-C I2C adapter
i2c-5 i2c i915 gmbus dpd I2C adapter
Now we can read back to ck505 configuration while running vendor firmware using smbus block read operation:
Now you put this information in the devicetree in coreboot
device pci 1f.3 on # SMbus
subsystemid 0x8086 0x5756
chip drivers/i2c/ck505
register "mask" = "{ 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff }"
register "regs" = "{ 0x41, 0x99, 0xff,
0xff, 0xff, 0x00, 0x00, 0x06,
0x03, 0x65, 0x83, 0x80, 0x15,
0xc0, 0x09, 0x00, 0x00, 0x00,
0x06, 0x00, 0xea }"
device i2c 69 on end
end
end
What works on this board?
- 2 x 4GB DDR3 DIMMs (using dual rank DIMMs)
- Core 2 CPU's (duo and quad) LGA775 CPU's (including modded LGA771 CPU's)
- PCI, PCIe, USB, PS2, Serial
- Native graphic init with VGA output
- S3 resume
TD;DL how do I use coreboot on the Intel DG41WV
Build a basic but working image with SeaBIOS for this board is really easy.
Run the following in the coreboot directory:
echo CONFIG_VENDOR_INTEL=y > .config
echo CONFIG_BOARD_INTEL_DG41WV=y >> .config
make olddefconfig
make
Now you can flash this to the flash chip. This can be done internally since the vendor firmware does not lock the SPI flash.
flashrom -p internal -w build/coreboot.rom
Feel free to ask any questions!
