FSP1.1 Braswell TempRaminit problems

Coreboot is migrating platforms from a romcc bootblock to C_ENVIRONMENT_BOOTBLOCK in which Cache-as-Ram is set up in the bootblock. When migrating Braswell, chromebooks featuring this SOC did not boot anymore while other boards did. Google uses a different FSP binary than the one present in the Intel Github FSP repository. Previously the romcc bootblock set […]

It’s back! Running a server of a single board computer.

Hi After about 6 months this blog is back online. The reason for it being offline is that that my Bananapi, featuring an allwinner A20, crashed. More specifically the SD card of which most of the software was run had fatally entered a state in which it started to have bad blocks that are marked […]

OLD: How to flash coreboot to the thinkpad x60 the proper way

What is so special about the x60 when running vendor bios? Vendor BIOS write protects its bootblock, which means the lowest 64K of the flash can’t be modified This is a problem since the first code that runs on the CPU comes from there and if we ever want to run coreboot the cpu must […]

OLD + UPDATE:Porting the Intel DG41WV and Intel 4 series DDR3 raminit to coreboot

This post will explain a bit how the Intel 4 series DDR3 raminit came to be and will introduce a new board that can make use of this code, namely the Intel DG41WV. DDR3 raminit In the past I have worked quite on a bit on the coreboot code that support the Intel 4 series […]