This post will review 2 llm options in emacs how I set them up. Ellama Your browser does not support the video tag. From ellama Ellama is a tool for interacting with large language models from Emacs. It allows you to ask questions and receive responses from the LLMs. Ellama can perform various tasks such as translation, code review, summarization, enhancing grammar/spelling or wording and more through the Emacs interface.

Aider + Claude Sonnet 3.5 This morning, I needed a timer to spend only 10 minutes reading a book. I searched for CLI tools but couldn't find anything immediately that suited my needs due to laziness. So, I decided to write one myself with the help of AI. Using Aider coupled with Claude Sonnet 3.5, I was able to get something working on the first try. Afterward, I added a few features:

This whitepaper will make the case that UEFI firmware and more specifically EDK2 based solutions, be it open or the more ubiquitous closed ones, are hurting business by driving up cost, delaying time to market, while at the same time are the cause of more security problems. This whitepaper will contrast this UEFI status quo with other existing solutions like LinuxBoot in combination with coreboot, which fully embrace open source development, are scoring better on all those metrics.

Rust in coreboot? Rust is a programming language with emphasis on performance, type safety and concurrency. It enforces memory safety at compile time. Unlike the C standard which is a 700+ page document, with a LOT of documented undefined behavior, rust has no undefined behavior unless the unsafe keyword is used. Zero cost abstractions make rust binaries very efficient in both size and execution, in places where C will have a hard time to be optimized (e.

This blog enty first appeared on the 9esec blog. A new toy to play with OpenBMC I wanted to play around with OpenBMC on a physical board and this article led me to the ASRock E3C246D4I. It's a not overly expensive Intel Coffee Lake board featuring an Aspeed AST2500 BMC. So the first thing I did was to compile OpenBMC. My computer was in for a quite a chore there.

This blog enty first appeared on the 9esec blog. FSP-T in open source projects X86 CPUs boot up in a very bare state. They execute the first instruction at the top of memory mapped flash in 16 bit real mode. DRAM is not avaible (AMD Zen CPUs are the exception) and the CPU typically has no memory addressable SRAM, a feature which is common on ARM SOCs. This makes running C code quite hard because you are required to have a stack.

This blog enty first appeared on the 9esec blog. I started working for 9elements in October 2020 and my first assignment was to get Intel CBnT working on the OCP Deltalake using coreboot firmware. Intel Converged Bootguard and TXT is a hardware assisted method to set up a root of trust. In this blog post I will discuss some of the changes needed in coreboot to get this working. Setting CBnT up properly was definitely a challenge, but the work did not stop there.

Coreboot is migrating platforms from a romcc bootblock to C_ENVIRONMENT_BOOTBLOCK in which Cache-as-Ram is set up in the bootblock. When migrating Braswell, chromebooks featuring this SOC did not boot anymore while other boards did. Google uses a different FSP binary than the one present in the Intel Github FSP repository. Previously the romcc bootblock set up caching of the ROM, located microcodes and performed the update before calling FSP TempRaminit.

This explains a bit of history on CAR in coreboot and how it works. Glossary CPU cache: CPU cache is a piece of fast memory used by the CPU to cache access to things accessed in the CPU's linear memory space. This includes for DRAM, PCI BARs, the boot flash. Cache-as-RAM/CAR: Using not memory mapped CPU cache as execution environment. XIP: Execute in place on a memory mapped (read only) medium.

What is so special about the x60 when running vendor bios? Vendor BIOS write protects its bootblock, which means the lowest 64K of the flash can’t be modified This is a problem since the first code that runs on the CPU comes from there and if we ever want to run coreboot the cpu must start with coreboot code. This write protection is set in the PBR (protect bios range) registers on the southbridge, there is currently no known way to change them back once they are locked by setting the SPI Configuration Lock-Down bit.